Semiconductor power devices have been in use since the early 1950s. They are specialized devices used as switches or rectifiers in power electronics circuits. Semiconductor power devices are characterized by their ability to withstand high voltages and large currents as well as the high temperatures associated with high power operation. For example, a switching voltage regulator will comprise two power devices that constantly switch on and off in a synchronized manner to regulate a voltage. The power devices in this situation need to sink system-level current in the on state, withstand the full potential of the power supply in the off state, and dissipate a large amount of heat. The ideal power device is able to operate in high power conditions, can rapidly switch between on and off states, and exhibits low thermal and on-state resistance.
A transistor structure referred to as a lateral diffusion metal oxide semiconductor (LDMOS) can be used to implement a power device. The “lateral diffusion” portion of this term refers to an extension of the drain region that is less strongly doped than the core drain region and that extends laterally away from the channel. This region is often referred to as the low-doped or lightly-doped drain (LDD) region. The LDD region allows the transistor to switch high voltages by making it able to withstand greater voltages in the off-state by absorbing portions of the electric field that would otherwise cause source-drain punch through, and to handle larger currents in the on-state by preventing a large potential drop from building up at the drain-body interface which would otherwise result in degradation of the device via the injection of hot carriers into the body of the device.
LDMOS transistors can include a gate shield that covers at least a portion of the LDD region and the gate electrode. The gate shield blocks the LDD region and the gate from the large current and voltage signals that are applied to the drain contact of the device. As such, the gate shield lowers the gate-to-drain capacitance of the LDMOS structure. In addition, the gate shield allows for a higher doping of the LDD because the LDD is less affected by large voltage signals applied to the drain contact of the device. As a result, the on-state resistance of the power device can decrease while preserving the device's breakdown and punch-through resistance.
FIG. 1 displays cross section 100 of an LDMOS transistor. The transistor comprises an active region 101 of a semiconductor wafer with an LDD 102 formed therein along with a drain region 103 and source region 104. A channel is formed between LDD 102 and source region 104 under the influence of a voltage applied to gate electrode 105. Gate electrode 105 is separated from the active region by a gate insulator 106. Gate shield 107 is coupled to source contact 108 and shields the gate electrode 105 and LDD 102 from drain contact 109. The source contact 108 of the power device is connected to ground. The gate shield is therefore also biased at ground to provide an adequate shield for LDD 102 and gate electrode 105 without disturbing the carriers in LDD 102. The gate shield is isolated from LDD 102 by an interlayer dielectric 110. The interlayer dielectric also provides a surface for additional circuity such as integrated wiring between portions of the same integrated circuit.